Cover for memory chips on a circuit board



FIG. 1 is a top plan view of a cover for memory chips on a circuit board showing my new design;

FIG. 2 is an inside view of the top portion, of the cover for memory chips on a circuit board;

FIG. 3 is a top plan view thereof;

FIG. 4 is a bottom plan view thereof;

FIG. 5 is a cross-sectional view thereof, taken along 5—5 of FIG. 1;

FIG. 6 is a front elevational view thereof;

FIG. 7 is a rear elevational view thereof;

FIG. 8 is an end elevational view thereof, the top portion is shown separately for clarity of illustration, the opposite end is a mirror image;

FIG. 9 is an end elevational view thereof;

FIG. 10 is a top perspective view thereof, on a reduced scale; and,

FIG. 11 is a cross-sectional view thereof, taken on line 11—11 of FIG. 1.

The broken line drawings of a circuit board in FIGS. 1, 4-7 and 9-11 is for illustrative purposes only and forms no part of the claimed design. 

The ornamental design for a cover for memory chips on a circuit board, as shown and described. 